A Design Verification Engineer Blog | dvtalk
Description: I’m a design verification engineer and this is where I keep my notes, my thoughts, my experiences or anything interesting that I think should belong here.
verification (367) vim (82) uvm (31) systemverilog (23) icdesign (3)
Hey there My Randoms Env Randoms Forcing Signals with Questasim/ModelSim Using Vim terminal Install tmux without root and Internet access UVM Randoms Using Plusargs in UVM Test uvm_pool example with Systemverilog semaphore How to use uvm_barrier and uvm_barrier_pool How to use uvm_event and uvm_event_pool How uvm factory actually works How to use uvm factory Differences between uvm test and uvm testbench top Systemverilog Randoms Systemverilog Streaming Operator Example std::randomize examples Choosing gran
I’m a design verification engineer and I’ve been in this industry for quite a while. Mostly this dvtalk blog is for keeping notes of what I know, and also problems big and small which I faced. My main task is verification so I work with systemverilog, uvm everyday and these are what I know the most. However, now and then, I also find myself struggling with formal verification, STA timing, design, and also scripting. Talking about scripting, I have been using csh and perl for a long time before switching to
OK, that’s it mates. Use the search box if you need anything. And if you cannot find what you need, well, later then. :D
A Design Verification Engineer Blog | dvtalk